1. Field of the Invention
Embodiments of the invention relate generally to a thread group address space that reduces virtual address computation circuitry for local memory space accesses.
2. Description of the Related Art
In a conventional system accesses to a local memory space by multiple threads may be performed in parallel by computing unique virtual addresses for each one of the threads in parallel. Computation of the unique virtual addresses may be a complex operation requiring dedicated circuitry for each one of the threads. When the data for the threads is cached, checking whether or not the data for each of the unique virtual addresses may also be performed in parallel, again requiring dedicated circuitry for the cache tag comparison operation. As the number of parallel threads increases, the amount of dedicated circuitry also increases. The performance of the unique virtual address computation and/or cache tag comparison may be reduced as the amount of time needed to perform the operations increases along with the increase in parallel threads.
Accordingly, what is needed in the art is an improved system and method for computing unique virtual addresses for each thread and performing the cache tag comparison.